1. Field of the Invention
The present invention relates generally to an information processing device in which a processor is employed. It particularly relates to an information processing device having a characteristic in a clock supply control method.
2. Related Background Art
In information processing devices including processors that process instructions, usually pipeline processing is carried out so as to improve the throughput of execution of instructions. As a common pipeline structure, a five-stage structure is used often, which is composed of an IF stage (instruction fetching stage), a DEC stage (instruction decoding stage), an EX stage (instruction execution stage), a MEM stage (memory access stage), and a WB stage (memory write-back stage). Normally, processes at the stages are executed while clocks of the same frequency are supplied to each stage shown above.
Furthermore, to improve the execution performance of the processor itself, the execution frequency is increased in many cases to enhance the processing speed. However, in the case where the clock frequency is increased in order to enhance the processing speed, the power consumption of the processor increases in proportion to the increase in the clock frequency. In the case of, for instance, portable devices in which processors are incorporated in particular, decreasing power consumption has been an object to be attained, while improving the processing performance has been demanded also, and solving this dilemma in technologies has been a significant task.
Conventionally, to decrease power consumption, a technique has been used in which when processing of a plurality of cycles is required in a certain stage, the clock supply to the other stages is suspended. In this technique, when processing of a plurality of cycles is carried out at the EX stage, the clock supply to the DEC stage and the IF stage can be suspended so as to suspend the processing at the DEC and IF stages. Therefore, in the pipeline, it is possible to reduce the power consumption at the stages where the processing is suspended.
By the same technique, it also is possible to reduce power consumption by suspending the clock supply to the EX, DEC, and IF stages when multi-cycle processing is carried out at the MEM stage.
However, by the above-described conventional problem-solving method, the clock supply to the EX stage is suspended when multi-cycle processing is carried out at the MEM stage, and hence, an instruction present at the EX stage is suspended after it is shifted to the EX stage. Therefore, during a cycle period in which multi-cycle processing is carried out at the MEM stage, even if an instruction that requires multi-cycle processing at the EX stage is inputted, the execution of the multi-cycle instruction at the EX stage cannot be started unless the execution at the MEM stage has been finished. Therefore, a problem arises in which the instruction for the execution at the EX stage is not completed yet when the execution at the MEM stage is finished, and the instruction of the EX stage cannot be shifted to the MEM stage immediately after the execution is completed at the MEM stage.
Processing timings in the foregoing example will be described in detail below, with reference to FIG. 1. FIG. 1 illustrates a pipeline state in which an instruction A causing seven-cycle processing to be performed at the MEM stage and an instruction B causing five-cycle processing to be performed at the EX stage are performed continuously.
The instruction A and the instruction B are shifted to the DEC stage of the pipeline in cycles 1-1 and 1-2, respectively, and the processing of the instruction A at the MEM stage is started in a cycle 1-3. At the same time, the instruction B is shifted to the EX stage in the cycle 1-3.
Since the instruction A requires seven-cycle processing at the MEM stage, the execution of the instruction A causes a pipe lock at the MEM stage in a period of cycles 1-4. In the conventional technique, since the clock supply to the EX stage is suspended until the processing at the MEM stage is finished, the EX stage clock is stopped during the period of cycles 1-4, as shown in FIG. 1. Therefore, at the EX state where the instruction B is to be processed, the processing cannot be continued since the EX stage clock is stopped.
The clock supply to the EX stage is resumed in a cycle 1-5 when the execution of the instruction A at the MEM stage has been finished, and therefore, the execution of the instruction B at the EX stage is resumed in the cycle 1-5.
In the case where the clock is supplied continuously to the EX stage, the instruction B can be executed even while the instruction A causes the processing to be performed at the MEM stage, and it is possible to input the instruction B to the MEM stage in the cycle 1-5 when the instruction A is shifted to the WB stage. However, by the conventional technique for decreasing power consumption, the execution at the EX stage is not resumed unless the instruction A is shifted to the WB stage, and hence, this actually results in that the input to the MEM stage is carried out in a cycle 1-7.
In other words, to decrease power consumption, a process that impairs the execution efficiency in the pipeline processing is performed. Furthermore, the above-described suspension of clock supply is carried out every time any instruction is performed in hardware. Therefore, in the case where, considering the characteristic of the program processing, the processing should be executed with a performance equal to that of the normal operation without the stop of the clock, it is necessary to separately provide a means to instruct continuous clock supply.